Dynamic random access memory (DRAM) technology is a core technology that occupies a large part of a silicon semiconductor market. Throughout the world, research on the next-generation DRAM has been actively carried out, and a higher density DRAM has been developed. Particularly, in order to reduce a size of a cell and increase a density, a gate length of a DRAM cell device is decreased. Reduction of the size of the cell device has a problem of the short channel effect. Due to the short channel effect, there is a problem in that drain current increases in an OFF state.
A metal-oxide-semiconductor field-effect transistor (MOSFET) according to a related art has a channel structure formed on a flat surface in which source/drain regions are formed at both sides of the channel. When the MOSFET having the conventional flat channel is applied to a DRAM technology using a 100 or less nm process, the short channel effect occurs in the MOSFET. In order to reduce a size of the MOSFET, conventionally, gate insulating layer thickness reduction, source/drain junction depth reduction, and channel doping density increase have to be followed. Since the gate length is decreased, a thickness of the gate insulating layer cannot be reduced as compared with a conventional logic MOSFET due to characteristics of the DRAM cell device. In addition, a depth of the source/drain cannot be relatively shortened, and this is an obstacle to reduce the size of the cell device. In addition, in order to prevent drain induced barrier lowering (DIBL) due to the reduction of the size of the cell, the doping density of the channel has to be increased. In this case, an electric field between the channel and the drain increases, and leakage current increases due to band-to-band tunneling. Off-state leakage current of drain current in the DRAM cell device has to be about 1 fA or less. Therefore, it is expected that reducing the gate length of the cell device of the MOSFET having the conventional flat channel to be about 70 nm or less is very difficult.
Research to solve the problem that occurs when a device having the conventional flat channel structure is used as the DRAM cell device has been actively carried out. A direction of the research is to develop and apply a three-dimensional device structure or a device structure having a channel that is not flat any more to the cell device. A representative device considered as the DRAM cell device is a device having a recessed channel structure and a bulk FinFET, and these are described as follows.
It is important for the memory cell device to reduce a cell area on a two-dimensional surface, increase on-current, and decrease off-current. The aforementioned recessed channel structure is a structure in which a length of an effective channel is increased while the two-dimensional surface area is not increased to suppress the short channel effect such as the DIBL. For example, a recessed structure for DRAM application is disclosed in a paper by Samsung Electronics in 2003 (J. Y. Kim et al., The breakthrough in data retention time of DRAM using recess-channel-array transistor (RCAT) for 88 nm feature size and beyond, in Proc. Symp. on VLSI Tech., p. 11, 2003). According to the paper, there is an advantage of significantly reducing the off-current by suppressing the short channel effect. However, there is a problem in that the on-current is significantly reduced due to a relatively long channel length and a narrow channel width. The reduction of the on-current may cause reduction of an operating speed of the DRAM. In addition, the recessed channel region may have two corners in a direction of the channel length, and when the channel doping density is changed at the corners, there is a problem in that the threshold voltage is significantly changed. Conventionally, a doping density only of the recessed channel in the device is high. However, in this case, the doping density affects the corner area. There is a worse problem in that when the recessed channel width is reduced as the size of the device is reduced, an etching profile adjacent to the recessed bottom cannot be easily controlled, and it is difficult to uniformly control the recessed channel depth. In addition, as the recessed channel width is reduced, sensitivity of the threshold voltage according to a change in the etching profile adjacent to the recessed bottom increases. Since the structure of the channel of the recessed channel device is concave, back-bias effects heavily occur. In addition, for negative substrate bias, an n-channel MOSFET (NMOS) has a problem in that a threshold voltage is significantly increased as compared with the flat channel. The recessed channel device has characteristics in that control ability of the gate electrode for the channel is degraded as compared with the flat channel device, and this is associated with the high substrate bias effects.
A structure having good control ability of the gate electrode for the channel is a double/triple-gate MOS structure. However, it is impossible to apply the double/triple-gate device implemented on a silicon on insulator (SOI) (referred to as SOI FinFET) as the DRAM cell device due to device characteristics. A body-tied double/triple-gate MOSFET having high practicality (see Korean Patent Registration No. 0458288, Korean Patent Registration No. 0471189, U.S. Patent Registration No. 6885055, Japanese Patent Application No. 2003-298051, U.S. patent application Ser. No. 10/358,981, Japanese Patent Application No. 2002-381448) is first published by the present inventor, and the present inventor called the structure a bulk FinFET. In the aforementioned structure, the channel is not recessed, and a channel is formed at an upper surface and both side surfaces of an active fence-shaped body, or a channel is formed to be adjacent to both side surfaces of a fence-shaped body. Therefore, the control ability of the gate for the channel is better than that of the conventional flat channel device. Therefore, the device has good ability to suppress the short channel effect and has low DIBL, and this is advantageous to reduction of the device size. In addition, the gate electrode has good control ability for the channel, so that there are hardly substrate bias effects. In terms of a two-dimensional surface, an area occupied by the cell is small, and an effect channel width is properly large, so that on-current increases, and this results in increase of the operating speed of the DRAM. When the bulk FinFET structure is applied to the DRAM cell device, there are many advantages.
However, when an n+ polycrystalline silicon gate is applied to a conventional n-type FinFET, a threshold voltage of the device is low, so that there is a disadvantage in that current in the OFF state increases. When a channel doping density is increased in order to increase the threshold voltage, leakage current due to band-to-band tunneling between a drain and the channel is increased, so that increasing the channel doping density is not effective. In order to solve the aforementioned problem, a negative wordline method may be applied. However, in this case, there are problems in that the negative wordline method is not general and peripheral circuits become complex. In order to increase the threshold voltage, a work function of the gate may be changed from n+ to p+. However, in this case, band bending increases at a drain region which overlaps with a gate electrode, so that there are problems in that GIDL is increased, and off-current is increased.
Therefore, the present assignee proposes a structure of the present invention in order to solve the aforementioned problems that occur when the conventional FinFET is applied to the DRAM.
When an SOI substrate is used to implement the FinFET, there are disadvantages in that the SOI substrate has more defects and more expensive than the bulk silicon substrate. The FinFET implemented on the SOI substrate has a floating body problem that is the problem of the conventional SOI device. In addition, a buried oxide (BOX) formed on the SOI substrate blocks heat generated from the device to be transferred to the substrate, so that characteristics of the device may be degraded. In addition, in the FinFET implemented on the SOI substrate, leakage current may increase due to the defects, so that the FinFET implemented on the SOI may not be applied to the DRAM which is sensitive to leakage current.
In order for the bulk FinFET to have DIBL of about 100 mV/V or less, a width of the body having a desired nano size has to be two-thirds of a gate length. Needless to say, the DIBL of the DRAM cell device has to be much smaller than 100 mV/V. Therefore, the width of the body is significantly reduced.
When the width of the body in the FinFET is reduced and the n+ polycrystalline silicon is used as the gate electrode, the threshold voltage is decreased. Therefore, when the gate voltage is 0V, drain current, that is, off-current increases. In order to solve the problem, a work function of the gate electrode has to be larger than that of the n+ polycrystalline silicon. For example, when it is changed into a p+ polycrystalline silicon gate, the threshold voltage is increased. Therefore, a threshold voltage required by the conventional DRAM can be obtained.
However, in this case, there is a problem in that GIDL per channel width increases at a given surface, and this results in decrease of a refresh time of the DRAM cell. There are two reasons why the GIDL increases. First, the p+ polycrystalline silicon or a gate having a high work function is used instead of the n+ polycrystalline silicon, so that the band structure is changed. Second, an effective area where a gate electrode and a drain per given surface area according to the FinFET device structure overlap is increased.
First, a case where the p+ polycrystalline silicon gate is used instead of the n+ polycrystalline gate to increase the GIDL is described. When the cell device is the NMOS, the p+ polycrystalline silicon gate which overlaps with an n+ drain has a work function higher than that of the n+ drain by a silicon energy band gap. When an equilibrium state in which gate bias is 0V is examined, an energy band of the drain region has to be tilted by the silicon band gap so that a Fermi level of the drain region is the same as that of the gate. The tilted energy band in the n+ drain region that overlaps with the p+ gate means existence of an electric field, and since a gradient thereof is great, electric field strength is also great. When the electric field strength is great, hole-electron pairs are produced around a surface of the drain region that overlaps with the gate, and electrons flow to the drain and drain current flows. When a drain voltage is increased, the energy band is further tilted, and leakage current due to the GIDL increases.
Next, a case where the effective area which generates the GIDL in the FinFET structure is increased is described. In the conventional flat channel, a channel width given to a two-dimensional surface becomes a practical channel width, and GIDL according to the channel width can be conventionally accepted. However, in the FinFET, in addition to the channel width given to the two-dimensional surface of the body, a channel is formed at a portion of both side surfaces thereof, and the gate electrode and the drain overlap along the channel width. Therefore, an area that may generate GIDL increases, and GIDL per unit cell increases. In order to solve the aforementioned problem, the present invention provides a device structure in which a work function of the gate electrode of the double/triple-gate MOSFET or FinFET is changed.
Hereinafter, a paper associated with a gate work function in double-gate structures according to a related art is described.
FIG. 1 illustrates a conventional device structure (see: S. Tiwari et al., International Electron Device Meeting, pp. 737-740, 1998). The device has an SOI structure in which a side gate 8 having a different work function is directly attached to a side surface of a main gate 7 and has a double-gate structure in which a gate having the same work function as that of the main gate 7 is disposed under a silicon film 20. In this structure, there is a disadvantage in that the side gate 8 is formed in a spacer shape and a practical gate length is increased. Particularly, the SOI device structure is not appropriate to be applied to a device that is sensitive to leakage current such as the DRAM. A lower gate is made of a material having the same work function as that of the main gate 7. This structure is proposed not to reduce the GIDL but suppress the short channel effect and increase a performance of the device.
FIG. 2 illustrates a double/gate device structure implemented on an SOI substrate (see: G. V. Reddy et al., IEEE Trans. on Nanotechnology, vol. 4, no. 2, pp. 260-268, March 2005) as a conventional device structure. In this structure, half an upper gate includes a main gate 7 having a high work function, and the other half thereof includes a gate 8 having a low work function. A lower gate includes a gate 8 having a low work function. The upper gate is originally made of p+ polycrystalline silicon. However, the half of the upper gate is changed into n+ to further suppress the short channel effect. In this paper, the SOI substrate is used as illustrated in FIG. 1. In addition, a single gate structure in which the upper gate is made of two materials having different work functions and the lower gate is doped with n+ is applied. Since the lower gate is n+, a threshold voltage is low, and therefore, the structure cannot be applied to the DRAM.
FIG. 3a illustrates a conventional device structure (see: S. Han et al., IEEE Trans. on Electron Devices, vol. 48, no. 9, pp. 2058-2064, September 2005) in which a gate 8 having a low work function is isolated from a gate 7 having a high work function by an insulating layer 10. The gate 8 can easily abandon a channel to a lower channel, so that an electrically abandoned inversion layer functions as a lightly doped drain (LDD). Since a channel structure is a flat channel structure, the channel structure has problems of the conventional flat channel structure. In addition, in the structure, GIDL needs not be reduced, and there is no associated description.
FIG. 3b illustrates a conventional device structure having a double-gate structure (see: A. A. Orouji et al., IEEE Trans. on Device and Materials Reliability, vol. 5, no. 3, pp. 509-514, September 2005). As the double-gate, a lower gate is an n+ gate, and an upper gate includes a p+ as a main gate and an n+ side gate electrically insulated from the main gate. In this document, it is described that the gate electrode structure is applied to improve the short channel effect and suppress generation of hot carriers. However, the structure is formed on the SOI substrate, the structure has problems of the SOI device. In addition, the side gate having a low work function of the upper gate is electrically isolated from the main gate having a high work function, so that there is a problem in that an area of the device is increased in the device manufacturing process.